Module lvds_bgr
d1_pac
0.0.31
Module lvds_bgr
Structs
Enums
Type Aliases
In d1_pac::ccu
Modules
apb_clk
audio_codec_adc_clk
audio_codec_bgr
audio_codec_dac_clk
avs_clk
ccu_fan
ccu_fan_gate
ce_bgr
ce_clk
clk27m_fan
cpu_axi_cfg
cpu_gating
csi_bgr
csi_clk
csi_master_clk
dbgsys_bgr
de_bgr
de_clk
di_bgr
di_clk
dma_bgr
dmic_bgr
dmic_clk
dpss_top_bgr
dram_bgr
dram_clk
dsi_bgr
dsi_clk
dsp_bgr
dsp_clk
emac_25m_clk
emac_bgr
fre_det_ctrl
fre_down_lim
fre_up_lim
g2d_bgr
g2d_clk
gpadc_bgr
hstimer_bgr
i2s2_asrc_clk
i2s_bgr
i2s_clk
iommu_bgr
irtx_bgr
irtx_clk
ledc_bgr
ledc_clk
lradc_bgr
lvds_bgr
mbus_clk
mbus_mat_clk_gating
msgbox_bgr
owa_bgr
owa_rx_clk
owa_tx_clk
pclk_fan
pll_audio0_bias
pll_audio0_ctrl
pll_audio0_pat0_ctrl
pll_audio0_pat1_ctrl
pll_audio1_bias
pll_audio1_ctrl
pll_audio1_pat0_ctrl
pll_audio1_pat1_ctrl
pll_cpu_bias
pll_cpu_ctrl
pll_cpu_tun
pll_ddr_bias
pll_ddr_ctrl
pll_ddr_pat0_ctrl
pll_ddr_pat1_ctrl
pll_lock_dbg_ctrl
pll_peri_bias
pll_peri_ctrl
pll_peri_pat0_ctrl
pll_peri_pat1_ctrl
pll_ve_bias
pll_ve_ctrl
pll_ve_pat0_ctrl
pll_ve_pat1_ctrl
pll_video0_bias
pll_video0_ctrl
pll_video0_pat0_ctrl
pll_video0_pat1_ctrl
pll_video1_bias
pll_video1_ctrl
pll_video1_pat0_ctrl
pll_video1_pat1_ctrl
psi_clk
pwm_bgr
riscv_cfg_bgr
riscv_clk
riscv_gating
smhc0_clk
smhc1_clk
smhc2_clk
smhc_bgr
spi0_clk
spi1_clk
spi_bgr
spinlock_bgr
tconlcd_bgr
tconlcd_clk
tcontv_bgr
tcontv_clk
ths_bgr
tpadc_bgr
tpadc_clk
tvd_bgr
tvd_clk
tve_bgr
tve_clk
twi_bgr
uart_bgr
usb0_clk
usb1_clk
usb_bgr
ve_bgr
ve_clk
Structs
RegisterBlock
Type Aliases
APB_CLK
AUDIO_CODEC_ADC_CLK
AUDIO_CODEC_BGR
AUDIO_CODEC_DAC_CLK
AVS_CLK
CCU_FAN
CCU_FAN_GATE
CE_BGR
CE_CLK
CLK27M_FAN
CPU_AXI_CFG
CPU_GATING
CSI_BGR
CSI_CLK
CSI_MASTER_CLK
DBGSYS_BGR
DE_BGR
DE_CLK
DI_BGR
DI_CLK
DMA_BGR
DMIC_BGR
DMIC_CLK
DPSS_TOP_BGR
DRAM_BGR
DRAM_CLK
DSI_BGR
DSI_CLK
DSP_BGR
DSP_CLK
EMAC_25M_CLK
EMAC_BGR
FRE_DET_CTRL
FRE_DOWN_LIM
FRE_UP_LIM
G2D_BGR
G2D_CLK
GPADC_BGR
HSTIMER_BGR
I2S2_ASRC_CLK
I2S_BGR
I2S_CLK
IOMMU_BGR
IRTX_BGR
IRTX_CLK
LEDC_BGR
LEDC_CLK
LRADC_BGR
LVDS_BGR
MBUS_CLK
MBUS_MAT_CLK_GATING
MSGBOX_BGR
OWA_BGR
OWA_RX_CLK
OWA_TX_CLK
PCLK_FAN
PLL_AUDIO0_BIAS
PLL_AUDIO0_CTRL
PLL_AUDIO0_PAT0_CTRL
PLL_AUDIO0_PAT1_CTRL
PLL_AUDIO1_BIAS
PLL_AUDIO1_CTRL
PLL_AUDIO1_PAT0_CTRL
PLL_AUDIO1_PAT1_CTRL
PLL_CPU_BIAS
PLL_CPU_CTRL
PLL_CPU_TUN
PLL_DDR_BIAS
PLL_DDR_CTRL
PLL_DDR_PAT0_CTRL
PLL_DDR_PAT1_CTRL
PLL_LOCK_DBG_CTRL
PLL_PERI_BIAS
PLL_PERI_CTRL
PLL_PERI_PAT0_CTRL
PLL_PERI_PAT1_CTRL
PLL_VE_BIAS
PLL_VE_CTRL
PLL_VE_PAT0_CTRL
PLL_VE_PAT1_CTRL
PLL_VIDEO0_BIAS
PLL_VIDEO0_CTRL
PLL_VIDEO0_PAT0_CTRL
PLL_VIDEO0_PAT1_CTRL
PLL_VIDEO1_BIAS
PLL_VIDEO1_CTRL
PLL_VIDEO1_PAT0_CTRL
PLL_VIDEO1_PAT1_CTRL
PSI_CLK
PWM_BGR
RISCV_CFG_BGR
RISCV_CLK
RISCV_GATING
SMHC0_CLK
SMHC1_CLK
SMHC2_CLK
SMHC_BGR
SPI0_CLK
SPI1_CLK
SPINLOCK_BGR
SPI_BGR
TCONLCD_BGR
TCONLCD_CLK
TCONTV_BGR
TCONTV_CLK
THS_BGR
TPADC_BGR
TPADC_CLK
TVD_BGR
TVD_CLK
TVE_BGR
TVE_CLK
TWI_BGR
UART_BGR
USB0_CLK
USB1_CLK
USB_BGR
VE_BGR
VE_CLK
?
Settings
Module
d1_pac
::
ccu
::
lvds_bgr
Copy item path
source
·
[
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Expand description
LVDS Bus Gating Reset Register
Structs
§
LVDS_BGR_SPEC
LVDS Bus Gating Reset Register
R
Register
lvds_bgr
reader
W
Register
lvds_bgr
writer
Enums
§
RST_A
Reset
Type Aliases
§
RST_R
Field
rst
reader - Reset
RST_W
Field
rst
writer - Reset