Struct d1_pac::iommu::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 94 fields
    pub iommu_reset: IOMMU_RESET,
    pub iommu_enable: IOMMU_ENABLE,
    pub iommu_bypass: IOMMU_BYPASS,
    pub iommu_auto_gating: IOMMU_AUTO_GATING,
    pub iommu_wbuf_ctrl: IOMMU_WBUF_CTRL,
    pub iommu_ooo_ctrl: IOMMU_OOO_CTRL,
    pub iommu_4kb_bdy_prt_ctrl: IOMMU_4KB_BDY_PRT_CTRL,
    pub iommu_ttb: IOMMU_TTB,
    pub iommu_tlb_enable: IOMMU_TLB_ENABLE,
    pub iommu_tlb_prefetch: IOMMU_TLB_PREFETCH,
    pub iommu_tlb_flush_enable: IOMMU_TLB_FLUSH_ENABLE,
    pub iommu_tlb_ivld_mode_sel: IOMMU_TLB_IVLD_MODE_SEL,
    pub iommu_tlb_ivld_sta_addr: IOMMU_TLB_IVLD_STA_ADDR,
    pub iommu_tlb_ivld_end_addr: IOMMU_TLB_IVLD_END_ADDR,
    pub iommu_tlb_ivld_addr: IOMMU_TLB_IVLD_ADDR,
    pub iommu_tlb_ivld_addr_mask: IOMMU_TLB_IVLD_ADDR_MASK,
    pub iommu_tlb_ivld_enable: IOMMU_TLB_IVLD_ENABLE,
    pub iommu_pc_ivld_mode_sel: IOMMU_PC_IVLD_MODE_SEL,
    pub iommu_pc_ivld_addr: IOMMU_PC_IVLD_ADDR,
    pub iommu_pc_ivld_sta_addr: IOMMU_PC_IVLD_STA_ADDR,
    pub iommu_pc_ivld_enable: IOMMU_PC_IVLD_ENABLE,
    pub iommu_pc_ivld_end_addr: IOMMU_PC_IVLD_END_ADDR,
    pub iommu_dm_aut_ctrl: [IOMMU_DM_AUT_CTRL; 8],
    pub iommu_dm_aut_ovwt: IOMMU_DM_AUT_OVWT,
    pub iommu_int_enable: IOMMU_INT_ENABLE,
    pub iommu_int_clr: IOMMU_INT_CLR,
    pub iommu_int_sta: IOMMU_INT_STA,
    pub iommu_int_err_addr_tlb: [IOMMU_INT_ERR_ADDR_TLB; 7],
    pub iommu_int_err_addr_l: [IOMMU_INT_ERR_ADDR_L; 2],
    pub iommu_int_err_data_tlb: [IOMMU_INT_ERR_DATA_TLB; 7],
    pub iommu_int_err_data_l: [IOMMU_INT_ERR_DATA_L; 2],
    pub iommu_lpg_int: [IOMMU_LPG_INT; 2],
    pub iommu_va: IOMMU_VA,
    pub iommu_va_data: IOMMU_VA_DATA,
    pub iommu_va_config: IOMMU_VA_CONFIG,
    pub iommu_pmu_enable: IOMMU_PMU_ENABLE,
    pub iommu_pmu_clr: IOMMU_PMU_CLR,
    pub iommu_pmu_access_low0: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high0: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low0: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high0: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low1: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high1: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low1: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high1: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low2: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high2: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low2: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high2: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low3: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high3: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low3: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high3: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low4: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high4: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low4: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high4: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low5: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high5: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low5: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high5: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low6: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high6: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low6: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high6: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low7: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high7: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low7: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high7: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_access_low8: IOMMU_PMU_ACCESS_LOW,
    pub iommu_pmu_access_high8: IOMMU_PMU_ACCESS_HIGH,
    pub iommu_pmu_hit_low8: IOMMU_PMU_HIT_LOW,
    pub iommu_pmu_hit_high8: IOMMU_PMU_HIT_HIGH,
    pub iommu_pmu_tl_low0: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high0: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml0: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low1: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high1: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml1: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low2: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high2: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml2: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low3: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high3: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml3: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low4: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high4: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml4: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low5: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high5: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml5: IOMMU_PMU_ML,
    pub iommu_pmu_tl_low6: IOMMU_PMU_TL_LOW,
    pub iommu_pmu_tl_high6: IOMMU_PMU_TL_HIGH,
    pub iommu_pmu_ml6: IOMMU_PMU_ML,
    /* private fields */

}
Expand description

Register block

Fields§

§iommu_reset: IOMMU_RESET

0x10 - IOMMU Reset Register

§iommu_enable: IOMMU_ENABLE

0x20 - IOMMU Enable Register

§iommu_bypass: IOMMU_BYPASS

0x30 - IOMMU Bypass Register

§iommu_auto_gating: IOMMU_AUTO_GATING

0x40 - IOMMU Auto Gating Register

§iommu_wbuf_ctrl: IOMMU_WBUF_CTRL

0x44 - IOMMU Write Buffer Control Register

§iommu_ooo_ctrl: IOMMU_OOO_CTRL

0x48 - IOMMU Out of Order Control Register

§iommu_4kb_bdy_prt_ctrl: IOMMU_4KB_BDY_PRT_CTRL

0x4c - IOMMU 4KB Boundary Protect Control Register

§iommu_ttb: IOMMU_TTB

0x50 - IOMMU Translation Table Base Register

§iommu_tlb_enable: IOMMU_TLB_ENABLE

0x60 - IOMMU TLB Enable Register

§iommu_tlb_prefetch: IOMMU_TLB_PREFETCH

0x70 - IOMMU TLB Prefetch Register

§iommu_tlb_flush_enable: IOMMU_TLB_FLUSH_ENABLE

0x80 - IOMMU TLB Flush Enable Register

§iommu_tlb_ivld_mode_sel: IOMMU_TLB_IVLD_MODE_SEL

0x84 - IOMMU TLB Invalidation Mode Select Register

§iommu_tlb_ivld_sta_addr: IOMMU_TLB_IVLD_STA_ADDR

0x88 - IOMMU TLB Invalidation Start Address Register

§iommu_tlb_ivld_end_addr: IOMMU_TLB_IVLD_END_ADDR

0x8c - IOMMU TLB Invalidation End Address Register

§iommu_tlb_ivld_addr: IOMMU_TLB_IVLD_ADDR

0x90 - IOMMU TLB Invalidation Address Register

§iommu_tlb_ivld_addr_mask: IOMMU_TLB_IVLD_ADDR_MASK

0x94 - IOMMU TLB Invalidation Address Mask Register

§iommu_tlb_ivld_enable: IOMMU_TLB_IVLD_ENABLE

0x98 - IOMMU TLB Invalidation Enable Register

§iommu_pc_ivld_mode_sel: IOMMU_PC_IVLD_MODE_SEL

0x9c - IOMMU PC Invalidation Mode Select Register

§iommu_pc_ivld_addr: IOMMU_PC_IVLD_ADDR

0xa0 - IOMMU PC Invalidation Address Register

§iommu_pc_ivld_sta_addr: IOMMU_PC_IVLD_STA_ADDR

0xa4 - IOMMU PC Invalidation Start Address Register

§iommu_pc_ivld_enable: IOMMU_PC_IVLD_ENABLE

0xa8 - IOMMU PC Invalidation Enable Register

§iommu_pc_ivld_end_addr: IOMMU_PC_IVLD_END_ADDR

0xac - IOMMU PC Invalidation End Address Register

§iommu_dm_aut_ctrl: [IOMMU_DM_AUT_CTRL; 8]

0xb0..0xd0 - IOMMU Domain Authority Control [i] Register

Software can set 15 different permission control types in IOMMU_DM_AUT_CTRL0-7. A default access control type is DOMAIN0. The read/write operation of DOMAIN1-15 is unlimited by default.

Software needs to set the index of the permission control domain corresponding to the page table item in the bit[7:4] of the Level2 page table, the default value is 0 (use domain 0), that is, the read/write operation is not controlled.

Setting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL0-7. All Level2 page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default.

§iommu_dm_aut_ovwt: IOMMU_DM_AUT_OVWT

0xd0 - IOMMU Domain Authority Overwrite Register

§iommu_int_enable: IOMMU_INT_ENABLE

0x100 - IOMMU Interrupt Enable Register

§iommu_int_clr: IOMMU_INT_CLR

0x104 - IOMMU Interrupt Clear Register

§iommu_int_sta: IOMMU_INT_STA

0x108 - IOMMU Interrupt Status Register

§iommu_int_err_addr_tlb: [IOMMU_INT_ERR_ADDR_TLB; 7]

0x110..0x12c - IOMMU Interrupt Error Address [i]

§iommu_int_err_addr_l: [IOMMU_INT_ERR_ADDR_L; 2]

0x130..0x138 - IOMMU Interrupt Error Address L[i]

§iommu_int_err_data_tlb: [IOMMU_INT_ERR_DATA_TLB; 7]

0x150..0x16c - IOMMU Interrupt Error Data [i] Register

§iommu_int_err_data_l: [IOMMU_INT_ERR_DATA_L; 2]

0x170..0x178 - IOMMU Interrupt Error Data L[i] Register

§iommu_lpg_int: [IOMMU_LPG_INT; 2]

0x180..0x188 - IOMMU L[i] Page Table Interrupt Register

§iommu_va: IOMMU_VA

0x190 - IOMMU Virtual Address Register

§iommu_va_data: IOMMU_VA_DATA

0x194 - IOMMU Virtual Address Data Register

§iommu_va_config: IOMMU_VA_CONFIG

0x198 - IOMMU Virtual Address Configuration Register

§iommu_pmu_enable: IOMMU_PMU_ENABLE

0x200 - IOMMU PMU Enable Register

§iommu_pmu_clr: IOMMU_PMU_CLR

0x210 - IOMMU PMU Clear Register

§iommu_pmu_access_low0: IOMMU_PMU_ACCESS_LOW

0x230 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high0: IOMMU_PMU_ACCESS_HIGH

0x234 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low0: IOMMU_PMU_HIT_LOW

0x238 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high0: IOMMU_PMU_HIT_HIGH

0x23c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low1: IOMMU_PMU_ACCESS_LOW

0x240 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high1: IOMMU_PMU_ACCESS_HIGH

0x244 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low1: IOMMU_PMU_HIT_LOW

0x248 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high1: IOMMU_PMU_HIT_HIGH

0x24c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low2: IOMMU_PMU_ACCESS_LOW

0x250 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high2: IOMMU_PMU_ACCESS_HIGH

0x254 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low2: IOMMU_PMU_HIT_LOW

0x258 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high2: IOMMU_PMU_HIT_HIGH

0x25c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low3: IOMMU_PMU_ACCESS_LOW

0x260 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high3: IOMMU_PMU_ACCESS_HIGH

0x264 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low3: IOMMU_PMU_HIT_LOW

0x268 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high3: IOMMU_PMU_HIT_HIGH

0x26c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low4: IOMMU_PMU_ACCESS_LOW

0x270 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high4: IOMMU_PMU_ACCESS_HIGH

0x274 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low4: IOMMU_PMU_HIT_LOW

0x278 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high4: IOMMU_PMU_HIT_HIGH

0x27c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low5: IOMMU_PMU_ACCESS_LOW

0x280 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high5: IOMMU_PMU_ACCESS_HIGH

0x284 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low5: IOMMU_PMU_HIT_LOW

0x288 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high5: IOMMU_PMU_HIT_HIGH

0x28c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low6: IOMMU_PMU_ACCESS_LOW

0x290 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high6: IOMMU_PMU_ACCESS_HIGH

0x294 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low6: IOMMU_PMU_HIT_LOW

0x298 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high6: IOMMU_PMU_HIT_HIGH

0x29c - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low7: IOMMU_PMU_ACCESS_LOW

0x2a0 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high7: IOMMU_PMU_ACCESS_HIGH

0x2a4 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low7: IOMMU_PMU_HIT_LOW

0x2a8 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high7: IOMMU_PMU_HIT_HIGH

0x2ac - IOMMU PMU Hit High [i] Register

§iommu_pmu_access_low8: IOMMU_PMU_ACCESS_LOW

0x2b0 - IOMMU PMU Access Low [i] Register

§iommu_pmu_access_high8: IOMMU_PMU_ACCESS_HIGH

0x2b4 - IOMMU PMU Access High [i] Register

§iommu_pmu_hit_low8: IOMMU_PMU_HIT_LOW

0x2b8 - IOMMU PMU Hit Low [i] Register

§iommu_pmu_hit_high8: IOMMU_PMU_HIT_HIGH

0x2bc - IOMMU PMU Hit High [i] Register

§iommu_pmu_tl_low0: IOMMU_PMU_TL_LOW

0x300 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high0: IOMMU_PMU_TL_HIGH

0x304 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml0: IOMMU_PMU_ML

0x308 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low1: IOMMU_PMU_TL_LOW

0x310 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high1: IOMMU_PMU_TL_HIGH

0x314 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml1: IOMMU_PMU_ML

0x318 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low2: IOMMU_PMU_TL_LOW

0x320 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high2: IOMMU_PMU_TL_HIGH

0x324 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml2: IOMMU_PMU_ML

0x328 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low3: IOMMU_PMU_TL_LOW

0x330 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high3: IOMMU_PMU_TL_HIGH

0x334 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml3: IOMMU_PMU_ML

0x338 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low4: IOMMU_PMU_TL_LOW

0x340 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high4: IOMMU_PMU_TL_HIGH

0x344 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml4: IOMMU_PMU_ML

0x348 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low5: IOMMU_PMU_TL_LOW

0x350 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high5: IOMMU_PMU_TL_HIGH

0x354 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml5: IOMMU_PMU_ML

0x358 - IOMMU Max Latency [i] Register

§iommu_pmu_tl_low6: IOMMU_PMU_TL_LOW

0x360 - IOMMU Total Latency Low [i] Register

§iommu_pmu_tl_high6: IOMMU_PMU_TL_HIGH

0x364 - IOMMU Total Latency High [i] Register

§iommu_pmu_ml6: IOMMU_PMU_ML

0x368 - IOMMU Max Latency [i] Register

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