Module d1_pac::pwm::cier

Capture IRQ Enable Register

Structs

• CIER_SPEC
  Capture IRQ Enable Register
• R
  Register cier reader
• W
  Register cier writer

Enums

• CFIE_A
  If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.
• CRIE_A
  If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.

Type Aliases

• CFIE_R
  Field cfie[0-7] reader - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.
• CFIE_W
  Field cfie[0-7] writer - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.
• CRIE_R
  Field crie[0-7] reader - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.
• CRIE_W
  Field crie[0-7] writer - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.