Struct d1_pac::riscv_cfg::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 20 fields
    pub riscv_sta_add0: RISCV_STA_ADD0,
    pub riscv_sta_add1: RISCV_STA_ADD1,
    pub rf1p_cfg: RF1P_CFG,
    pub rom_cfg: ROM_CFG,
    pub wakeup_en: WAKEUP_EN,
    pub wakeup_mask: [WAKEUP_MASK; 5],
    pub ts_tmode_sel: TS_TMODE_SEL,
    pub sram_addr_twist: SRAM_ADDR_TWIST,
    pub work_mode: WORK_MODE,
    pub retite_pc0: RETITE_PC0,
    pub retite_pc1: RETITE_PC1,
    pub irq_mode: [IRQ_MODE; 5],
    pub riscv_axi_pmu_ctrl: RISCV_AXI_PMU_CTRL,
    pub riscv_axi_pmu_prd: RISCV_AXI_PMU_PRD,
    pub riscv_axi_pmu_lat_rd: RISCV_AXI_PMU_LAT_RD,
    pub riscv_axi_pmu_lat_wr: RISCV_AXI_PMU_LAT_WR,
    pub riscv_axi_pmu_req_rd: RISCV_AXI_PMU_REQ_RD,
    pub riscv_axi_pmu_req_wr: RISCV_AXI_PMU_REQ_WR,
    pub riscv_axi_pmu_bw_rd: RISCV_AXI_PMU_BW_RD,
    pub riscv_axi_pmu_bw_wr: RISCV_AXI_PMU_BW_WR,
    /* private fields */

}
Expand description

Register block

Fields§

§riscv_sta_add0: RISCV_STA_ADD0

0x04 - RISCV Start Address0 Register

§riscv_sta_add1: RISCV_STA_ADD1

0x08 - RISCV Start Address1 Register

§rf1p_cfg: RF1P_CFG

0x10 - RF1P Configuration Register

§rom_cfg: ROM_CFG

0x1c - ROM Configuration Register

§wakeup_en: WAKEUP_EN

0x20 - Wakeup Enable Register

§wakeup_mask: [WAKEUP_MASK; 5]

0x24..0x38 - Wakeup Mask Register

§ts_tmode_sel: TS_TMODE_SEL

0x40 - Timestamp Test Mode Select Register

§sram_addr_twist: SRAM_ADDR_TWIST

0x44 - SRAM Address Twist Register

§work_mode: WORK_MODE

0x48 - Work Mode Register

§retite_pc0: RETITE_PC0

0x50 - Retire PC0 Register

§retite_pc1: RETITE_PC1

0x54 - Retire PC1 Register

§irq_mode: [IRQ_MODE; 5]

0x60..0x74 - IRQ Mode Register

§riscv_axi_pmu_ctrl: RISCV_AXI_PMU_CTRL

0x104 - RISCV AXI PMU Control Register

§riscv_axi_pmu_prd: RISCV_AXI_PMU_PRD

0x108 - RISCV AXI PMU Period Register

§riscv_axi_pmu_lat_rd: RISCV_AXI_PMU_LAT_RD

0x10c - RISCV AXI PMU Read Latency Register

§riscv_axi_pmu_lat_wr: RISCV_AXI_PMU_LAT_WR

0x110 - RISCV AXI PMU Write Latency Register

§riscv_axi_pmu_req_rd: RISCV_AXI_PMU_REQ_RD

0x114 - RISCV AXI PMU Read Request Register

§riscv_axi_pmu_req_wr: RISCV_AXI_PMU_REQ_WR

0x118 - RISCV AXI PMU Write Request Register

§riscv_axi_pmu_bw_rd: RISCV_AXI_PMU_BW_RD

0x11c - RISCV AXI PMU Read Bandwidth Register

§riscv_axi_pmu_bw_wr: RISCV_AXI_PMU_BW_WR

0x120 - RISCV AXI PMU Write Bandwidth Register

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