Struct d1_pac::spi_dbi::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 26 fields
    pub spi_gcr: SPI_GCR,
    pub spi_tcr: SPI_TCR,
    pub spi_ier: SPI_IER,
    pub spi_isr: SPI_ISR,
    pub spi_fcr: SPI_FCR,
    pub spi_fsr: SPI_FSR,
    pub spi_wcr: SPI_WCR,
    pub spi_samp_dl: SPI_SAMP_DL,
    pub spi_mbc: SPI_MBC,
    pub spi_mtc: SPI_MTC,
    pub spi_bcc: SPI_BCC,
    pub spi_batc: SPI_BATC,
    pub spi_ba_ccr: SPI_BA_CCR,
    pub spi_tbr: SPI_TBR,
    pub spi_rbr: SPI_RBR,
    pub spi_ndma_mode_ctl: SPI_NDMA_MODE_CTL,
    pub dbi_ctl_0: DBI_CTL_0,
    pub dbi_ctl_1: DBI_CTL_1,
    pub dbi_ctl_2: DBI_CTL_2,
    pub dbi_timer: DBI_TIMER,
    pub dbi_video_szie: DBI_VIDEO_SZIE,
    pub dbi_int: DBI_INT,
    pub dbi_debug_0: DBI_DEBUG_0,
    pub dbi_debug_1: DBI_DEBUG_1,
    pub spi_txd: SPI_TXD,
    pub spi_rxd: SPI_RXD,
    /* private fields */

}
Expand description

Register block

Fields§

§spi_gcr: SPI_GCR

0x04 - SPI Global Control Register

§spi_tcr: SPI_TCR

0x08 - SPI Transfer Control Register

§spi_ier: SPI_IER

0x10 - SPI Interrupt Control Register

§spi_isr: SPI_ISR

0x14 - SPI Interrupt Status Register

§spi_fcr: SPI_FCR

0x18 - SPI FIFO Control Register

§spi_fsr: SPI_FSR

0x1c - SPI FIFO Status Register

§spi_wcr: SPI_WCR

0x20 - SPI Wait Clock Register

§spi_samp_dl: SPI_SAMP_DL

0x28 - SPI Sample Delay Control Register

§spi_mbc: SPI_MBC

0x30 - SPI Master Burst Counter Register

§spi_mtc: SPI_MTC

0x34 - SPI Master Transmit Counter Register

§spi_bcc: SPI_BCC

0x38 - SPI Master Burst Control Register

§spi_batc: SPI_BATC

0x40 - SPI Bit-Aligned Transfer Configure Register

§spi_ba_ccr: SPI_BA_CCR

0x44 - SPI Bit-Aligned Clock Configuration Register

§spi_tbr: SPI_TBR

0x48 - SPI TX Bit Register

VTB [31:0]: The Value of the Transmit Bits

§spi_rbr: SPI_RBR

0x4c - SPI RX Bit Register

VRB [31:0]: The Value of the Receive Bits

§spi_ndma_mode_ctl: SPI_NDMA_MODE_CTL

0x88 - SPI Normal DMA Mode Control Register

§dbi_ctl_0: DBI_CTL_0

0x100 - DBI Control Register 0

§dbi_ctl_1: DBI_CTL_1

0x104 - DBI Control Register 1

§dbi_ctl_2: DBI_CTL_2

0x108 - DBI Control Register 2

§dbi_timer: DBI_TIMER

0x10c - DBI Timer Control Register

§dbi_video_szie: DBI_VIDEO_SZIE

0x110 - DBI Video Size Configuration Register

§dbi_int: DBI_INT

0x120 - DBI Interrupt Register

§dbi_debug_0: DBI_DEBUG_0

0x124 - DBI BEBUG 0 Register

§dbi_debug_1: DBI_DEBUG_1

0x128 - DBI BEBUG 1 Register

§spi_txd: SPI_TXD

0x200 - SPI TX Data Register

TDATA [31:0]: Transmit Data

§spi_rxd: SPI_RXD

0x300 - SPI RX Data Register

RDATA [31:0]: Receive Data

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