Struct d1_pac::tpadc::tp_int_fifo_ctrl::TP_INT_FIFO_CTRL_SPEC

pub struct TP_INT_FIFO_CTRL_SPEC;

TP Interrupt FIFO Control Register

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see tp_int_fifo_ctrl module

Trait Implementations

impl Readable for TP_INT_FIFO_CTRL_SPEC

read() method returns tp_int_fifo_ctrl::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for TP_INT_FIFO_CTRL_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for TP_INT_FIFO_CTRL_SPEC

reset() method sets tp_int_fifo_ctrl to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <tpadc::tp_int_fifo_ctrl::TP_INT_FIFO_CTRL_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for TP_INT_FIFO_CTRL_SPEC

write(|w| ..) method takes tp_int_fifo_ctrl::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <tpadc::tp_int_fifo_ctrl::TP_INT_FIFO_CTRL_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <tpadc::tp_int_fifo_ctrl::TP_INT_FIFO_CTRL_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1