Struct d1_pac::tvd0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 31 fields
    pub tvd_en: TVD_EN,
    pub tvd_mode: TVD_MODE,
    pub tvd_clamp_agc1: TVD_CLAMP_AGC1,
    pub tvd_clamp_agc2: TVD_CLAMP_AGC2,
    pub tvd_hlock1: TVD_HLOCK1,
    pub tvd_hlock2: TVD_HLOCK2,
    pub tvd_hlock3: TVD_HLOCK3,
    pub tvd_hlock4: TVD_HLOCK4,
    pub tvd_hlock5: TVD_HLOCK5,
    pub tvd_vlock1: TVD_VLOCK1,
    pub tvd_vlock2: TVD_VLOCK2,
    pub tvd_clock1: TVD_CLOCK1,
    pub tvd_clock2: TVD_CLOCK2,
    pub tvd_yc_sep1: TVD_YC_SEP1,
    pub tvd_yc_sep2: TVD_YC_SEP2,
    pub tvd_enhance1: TVD_ENHANCE1,
    pub tvd_enhance2: TVD_ENHANCE2,
    pub tvd_enhance3: TVD_ENHANCE3,
    pub tvd_wb1: TVD_WB1,
    pub tvd_wb2: TVD_WB2,
    pub tvd_wb3: TVD_WB3,
    pub tvd_wb4: TVD_WB4,
    pub tvd_irq_ctl: TVD_IRQ_CTL,
    pub tvd_irq_status: TVD_IRQ_STATUS,
    pub tvd_debug1: TVD_DEBUG1,
    pub tvd_status1: TVD_STATUS1,
    pub tvd_status2: TVD_STATUS2,
    pub tvd_status3: TVD_STATUS3,
    pub tvd_status4: TVD_STATUS4,
    pub tvd_status5: TVD_STATUS5,
    pub tvd_status6: TVD_STATUS6,
    /* private fields */

}
Expand description

Register block

Fields§

§tvd_en: TVD_EN

0x00 - TVD MODULE CONTROL Register

§tvd_mode: TVD_MODE

0x04 - TVD MODE CONTROL Register

§tvd_clamp_agc1: TVD_CLAMP_AGC1

0x08 - TVD CLAMP And AGC CONTROL Register1

§tvd_clamp_agc2: TVD_CLAMP_AGC2

0x0c - TVD CLAMP And AGC CONTROL Register2

§tvd_hlock1: TVD_HLOCK1

0x10 - TVD HLOCK CONTROL Register1

§tvd_hlock2: TVD_HLOCK2

0x14 - TVD HLOCK CONTROL Register2

§tvd_hlock3: TVD_HLOCK3

0x18 - TVD HLOCK CONTROL Register3

§tvd_hlock4: TVD_HLOCK4

0x1c - TVD HLOCK CONTROL Register4

§tvd_hlock5: TVD_HLOCK5

0x20 - TVD HLOCK CONTROL Register5

§tvd_vlock1: TVD_VLOCK1

0x24 - TVD VLOCK CONTROL Register1

§tvd_vlock2: TVD_VLOCK2

0x28 - TVD VLOCK CONTROL Register2

§tvd_clock1: TVD_CLOCK1

0x30 - TVD CHROMA LOCK CONTROL Register1

§tvd_clock2: TVD_CLOCK2

0x34 - TVD CHROMA LOCK CONTROL Register2

§tvd_yc_sep1: TVD_YC_SEP1

0x40 - TVD YC SEPERATION CONROL Register1

§tvd_yc_sep2: TVD_YC_SEP2

0x44 - TVD YC SEPERATION CONROL Register2

§tvd_enhance1: TVD_ENHANCE1

0x50 - TVD ENHANCEMENT CONTROL Register1

§tvd_enhance2: TVD_ENHANCE2

0x54 - TVD ENHANCEMENT CONTROL Register2

§tvd_enhance3: TVD_ENHANCE3

0x58 - TVD ENHANCEMENT CONTROL Register3

§tvd_wb1: TVD_WB1

0x60 - TVD WB DMA CONTROL Register1

§tvd_wb2: TVD_WB2

0x64 - TVD WB DMA CONTROL Register2

§tvd_wb3: TVD_WB3

0x68 - TVD WB DMA CONTROL Register3

§tvd_wb4: TVD_WB4

0x6c - TVD WB DMA CONTROL Register4

§tvd_irq_ctl: TVD_IRQ_CTL

0x80 - TVD DMA Interrupt Control Register

§tvd_irq_status: TVD_IRQ_STATUS

0x90 - TVD DMA Interrupt Status Register

§tvd_debug1: TVD_DEBUG1

0x100 - TVD DEBUG CONTROL Register1

§tvd_status1: TVD_STATUS1

0x180 - TVD DEBUG STATUS Register1

§tvd_status2: TVD_STATUS2

0x184 - TVD DEBUG STATUS Register2

§tvd_status3: TVD_STATUS3

0x188 - TVD DEBUG STATUS Register3

§tvd_status4: TVD_STATUS4

0x18c - TVD DEBUG STATUS Register4

§tvd_status5: TVD_STATUS5

0x190 - TVD DEBUG STATUS Register5

§tvd_status6: TVD_STATUS6

0x194 - TVD DEBUG STATUS Register6

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