Struct d1_pac::tvd_top::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 18 fields
    pub tvd_top_map: TVD_TOP_MAP,
    pub tvd_3d_ctl1: TVD_3D_CTL1,
    pub tvd_3d_ctl2: TVD_3D_CTL2,
    pub tvd_3d_ctl3: TVD_3D_CTL3,
    pub tvd_3d_ctl4: TVD_3D_CTL4,
    pub tvd_3d_ctl5: TVD_3D_CTL5,
    pub tvd_top_ctl0: TVD_TOP_CTL,
    pub tvd_adc_ctl0: TVD_ADC_CTL,
    pub tvd_adc_cfg0: TVD_ADC_CFG,
    pub tvd_top_ctl1: TVD_TOP_CTL,
    pub tvd_adc_ctl1: TVD_ADC_CTL,
    pub tvd_adc_cfg1: TVD_ADC_CFG,
    pub tvd_top_ctl2: TVD_TOP_CTL,
    pub tvd_adc_ctl2: TVD_ADC_CTL,
    pub tvd_adc_cfg2: TVD_ADC_CFG,
    pub tvd_top_ctl3: TVD_TOP_CTL,
    pub tvd_adc_ctl3: TVD_ADC_CTL,
    pub tvd_adc_cfg3: TVD_ADC_CFG,
    /* private fields */

}
Expand description

Register block

Fields§

§tvd_top_map: TVD_TOP_MAP

0x00 - TVD TOP MAP Register

§tvd_3d_ctl1: TVD_3D_CTL1

0x08 - TVD 3D DMA CONTROL Register1

§tvd_3d_ctl2: TVD_3D_CTL2

0x0c - TVD 3D DMA CONTROL Register2

§tvd_3d_ctl3: TVD_3D_CTL3

0x10 - TVD 3D DMA CONTROL Register3

§tvd_3d_ctl4: TVD_3D_CTL4

0x14 - TVD 3D DMA CONTROL Register4

§tvd_3d_ctl5: TVD_3D_CTL5

0x18 - TVD 3D DMA CONTROL Register5

§tvd_top_ctl0: TVD_TOP_CTL

0x24 - TVD TOP CONTROL Register

§tvd_adc_ctl0: TVD_ADC_CTL

0x28 - TVD ADC CONTROL Register

§tvd_adc_cfg0: TVD_ADC_CFG

0x2c - TVD ADC CONFIGURATION Register

§tvd_top_ctl1: TVD_TOP_CTL

0x44 - TVD TOP CONTROL Register

§tvd_adc_ctl1: TVD_ADC_CTL

0x48 - TVD ADC CONTROL Register

§tvd_adc_cfg1: TVD_ADC_CFG

0x4c - TVD ADC CONFIGURATION Register

§tvd_top_ctl2: TVD_TOP_CTL

0x64 - TVD TOP CONTROL Register

§tvd_adc_ctl2: TVD_ADC_CTL

0x68 - TVD ADC CONTROL Register

§tvd_adc_cfg2: TVD_ADC_CFG

0x6c - TVD ADC CONFIGURATION Register

§tvd_top_ctl3: TVD_TOP_CTL

0x84 - TVD TOP CONTROL Register

§tvd_adc_ctl3: TVD_ADC_CTL

0x88 - TVD ADC CONTROL Register

§tvd_adc_cfg3: TVD_ADC_CFG

0x8c - TVD ADC CONFIGURATION Register

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