Module d1_pac::twi::twi_drv_bus_ctrl

TWI_DRV Bus Control Register

Structs

• R
  Register twi_drv_bus_ctrl reader
• TWI_DRV_BUS_CTRL_SPEC
  TWI_DRV Bus Control Register
• W
  Register twi_drv_bus_ctrl writer

Enums

• CLK_COUNT_MODE_AW
  Value on reset: 0
• CLK_DUTY_A
  Setting duty cycle of clock as master

Type Aliases

• CLK_COUNT_MODE_W
  Field clk_count_mode writer -
• CLK_DUTY_R
  Field clk_duty reader - Setting duty cycle of clock as master
• CLK_DUTY_W
  Field clk_duty writer - Setting duty cycle of clock as master
• CLK_M_R
  Field clk_m reader -
• CLK_M_W
  Field clk_m writer -
• CLK_N_R
  Field clk_n reader -
• CLK_N_W
  Field clk_n writer -
• SCL_MOE_R
  Field scl_moe reader - SCL manual output enable
• SCL_MOE_W
  Field scl_moe writer - SCL manual output enable
• SCL_MOV_R
  Field scl_mov reader - SCL manual output value
• SCL_MOV_W
  Field scl_mov writer - SCL manual output value
• SCL_STA_R
  Field scl_sta reader - SCL current status
• SDA_MOE_R
  Field sda_moe reader - SDA manual output enable
• SDA_MOE_W
  Field sda_moe writer - SDA manual output enable
• SDA_MOV_R
  Field sda_mov reader - SDA manual output value
• SDA_MOV_W
  Field sda_mov writer - SDA manual output value
• SDA_STA_R
  Field sda_sta reader - SDA current status