Trait embedded_hal_async::i2c::I2c

pub trait I2c<A: AddressMode = SevenBitAddress>: ErrorType {
    // Required method
    async fn transaction(
        &mut self,
        address: A,
        operations: &mut [Operation<'_>],
    ) -> Result<(), Self::Error>;

    // Provided methods
    async fn read(
        &mut self,
        address: A,
        read: &mut [u8],
    ) -> Result<(), Self::Error> { ... }
    async fn write(
        &mut self,
        address: A,
        write: &[u8],
    ) -> Result<(), Self::Error> { ... }
    async fn write_read(
        &mut self,
        address: A,
        write: &[u8],
        read: &mut [u8],
    ) -> Result<(), Self::Error> { ... }
}

Async i2c

Required Methods

async fn transaction( &mut self, address: A, operations: &mut [Operation<'_>], ) -> Result<(), Self::Error>

Execute the provided operations on the I2C bus as a single transaction.

Transaction contract:

• Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.

• Data from adjacent operations of the same type are sent after each other without an SP or SR.

• Between adjacent operations of a different type an SR and SAD+R/W is sent.

• After executing the last operation an SP is sent automatically.

• If the last operation is a Read the master does not send an acknowledge for the last byte.

• ST = start condition

• SAD+R/W = slave address followed by bit 1 to indicate reading or 0 to indicate writing

• SR = repeated start condition

• SP = stop condition

Provided Methods

async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>

Reads enough bytes from slave with address to fill buffer

I2C Events (contract)

Master: ST SAD+R        MAK    MAK ...    NMAK SP
Slave:           SAK B0     B1     ... BN

Where

• ST = start condition
• SAD+R = slave address followed by bit 1 to indicate reading
• SAK = slave acknowledge
• Bi = ith byte of data
• MAK = master acknowledge
• NMAK = master no acknowledge
• SP = stop condition

async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>

Writes bytes to slave with address address

I2C Events (contract)

Master: ST SAD+W     B0     B1     ... BN     SP
Slave:           SAK    SAK    SAK ...    SAK

Where

• ST = start condition
• SAD+W = slave address followed by bit 0 to indicate writing
• SAK = slave acknowledge
• Bi = ith byte of data
• SP = stop condition

async fn write_read( &mut self, address: A, write: &[u8], read: &mut [u8], ) -> Result<(), Self::Error>

Writes bytes to slave with address address and then reads enough bytes to fill read in a single transaction.

I2C Events (contract)

Master: ST SAD+W     O0     O1     ... OM     SR SAD+R        MAK    MAK ...    NMAK SP
Slave:           SAK    SAK    SAK ...    SAK          SAK I0     I1     ... IN

Where

• ST = start condition
• SAD+W = slave address followed by bit 0 to indicate writing
• SAK = slave acknowledge
• Oi = ith outgoing byte of data
• SR = repeated start condition
• SAD+R = slave address followed by bit 1 to indicate reading
• Ii = ith incoming byte of data
• MAK = master acknowledge
• NMAK = master no acknowledge
• SP = stop condition

Object Safety

This trait is not object safe.

Implementations on Foreign Types

impl<A: AddressMode, T: I2c<A>> I2c<A> for &mut T

async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>

async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>

async fn write_read( &mut self, address: A, write: &[u8], read: &mut [u8], ) -> Result<(), Self::Error>

async fn transaction( &mut self, address: A, operations: &mut [Operation<'_>], ) -> Result<(), Self::Error>

Implementors